Methods and apparatus of creating airgap in dielectric layers for the reduction of rc delay

ABSTRACT

A method and apparatus for generating air gaps in a dielectric material of an interconnect structure. One embodiment provides a method for forming a semiconductor structure comprising depositing a first dielectric layer on a substrate, forming trenches in the first dielectric layer, filling the trenches with a conductive material, planarizing the conductive material to expose the first dielectric layer, depositing a dielectric barrier film on the conductive material and exposed first dielectric layer, depositing a hard mask layer over the dielectric barrier film, forming a pattern in the dielectric barrier film and the hard mask layer to expose selected regions of the substrate, oxidizing at least a portion of the first dielectric layer in the selected region of the substrate, removing oxidized portion of the first dielectric layer to form reversed trenches around the conductive material, and forming air gaps in the reversed trenches while depositing a second dielectric material in the reversed trenches.

CROSS REFERENCE TO RELATED PATENT APPLICATIONS

This application is a Divisional Application of a pending U.S.Provisional patent application Ser. No. 11/869,396 (Attorney Docket No.12174L), filed Oct. 9, 2007, which is herein incorporated by reference.

BACKGROUND OF THE INVENTION

1. Field of the Invention

Embodiments of the present invention generally relate to the fabricationof integrated circuits. More particularly, embodiments of the presentinvention relate to methods for forming multilevel interconnectstructures that include dielectric materials having low dielectricconstants.

2. Description of the Related Art

Integrated circuit geometries have dramatically decreased in size sincesuch devices were first introduced several decades ago. Since then,integrated circuits have generally followed the two year/half-size rule(often called Moore's Law), which means that the number of devices on achip doubles every two years. Today's fabrication facilities areroutinely producing devices having 0.1 μm feature sizes, and tomorrow'sfacilities soon will be producing devices having even smaller featuresizes.

The continued reduction in device geometries has generated a demand forfilms having low dielectric constant (k) values because the capacitivecoupling between adjacent metal lines must be reduced to further reducethe size of devices on integrated circuits. For example, the scaling ofCMOS (complementary field-effect transistor) device requires acontinuous reduction to the RC (resistive capacitive) delay in the BEOL(Back-End-Of-the-Line) interconnects. To meet this requirement thedielectric constant (k) of the insulating layers used in the BEOL mustbe further reduced.

Over the last 10-15 years, the semiconductor industry went through manycycles in reducing the dielectric constant of the insulating layers,from using pure silicon dioxide (SiO₂) with k=4.2 to the present day ofporous carbon doped silicon oxide film, which comprises silicon, carbon,oxygen and hydrogen (commonly referred as SiCOH), with k=2.4.Conventional techniques generally use two methods to reduce k: (1)adding carbon to the SiO₂ matrix and (2) adding porosity. However, thesemethods of reducing result in lower mechanical properties compared tothat of SiO₂. These low mechanical properties, such as low modulus, andlow hardness, made it difficult to integrate such films with metallines, for example copper lines, in the dual damascene flow, which isgenerally used in forming BEOL interconnects. Additionally, futuretechnologies (32 nm node and beyond) will require higher porosity in theSiCOH films. However, the loss of mechanical properties with higherporosity would indicate a lower limit of k˜2.0 for this type of films.

Therefore, in view of the continuing decrease in integrated circuitfeature sizes and existing problems in the conventional methods, thereremains a need for a method of forming dielectric layers havingdielectric constants lower than 2.0

SUMMARY OF THE INVENTION

The present invention generally provides methods for forming air gaps ina dielectric around conductive lines in the interconnect materials.

One embodiment provides a method for forming a semiconductor structurecomprising depositing a first dielectric layer on a substrate, formingtrenches in the first dielectric layer, filling the trenches with aconductive material, planarizing the conductive material to expose thefirst dielectric layer, depositing a dielectric barrier film on theconductive material and exposed first dielectric layer, depositing ahard mask layer over the dielectric barrier film, forming a pattern inthe dielectric barrier film and the hard mask layer to expose selectedregions of the substrate, oxidizing at least a portion of the firstdielectric layer in the selected region of the substrate, removingoxidized portion of the first dielectric layer to form reversed trenchesaround the conductive material, and forming air gaps in the reversedtrenches while depositing a second dielectric material in the reversedtrenches.

In another embodiment, a porous dielectric material is used to form thetrenches and an electron beam treatment is used to oxidize the porousdielectric material.

Yet another embodiment provides a method for forming a dielectricstructure having air gaps comprising depositing a first dielectric layeron a substrate, depositing a second dielectric layer on the firstdielectric layer, forming trench-via structures in the first and seconddielectric layer, wherein vias are formed in the first dielectric layerand trenches are formed in the second dielectric layer, filling thetrench-via structures with a conductive material, planarizing theconductive material to expose the second dielectric layer, depositing adielectric barrier film on the conductive material and exposed seconddielectric layer, forming a pattern in the dielectric barrier film andthe hard mask layer to expose selected regions of the substrate,removing the second dielectric layer in the selected regions of thesubstrate to form reversed trenches around the conductive materialfilled in the trenches, and forming air gaps in the reversed trencheswhile depositing a dielectric material in the reversed trenches.

BRIEF DESCRIPTION OF THE DRAWINGS

So that the manner in which the above recited features of the presentinvention can be understood in detail, a more particular description ofthe invention, briefly summarized above, may be had by reference toembodiments, some of which are illustrated in the appended drawings. Itis to be noted, however, that the appended drawings illustrate onlytypical embodiments of this invention and are therefore not to beconsidered limiting of its scope, for the invention may admit to otherequally effective embodiments.

FIG. 1 is a flow chart showing a method for forming air gaps ininterconnect in accordance with one embodiment of the present invention.

FIG. 2A is a flow chart showing a process sequence for formingtrench-via structures in accordance with one embodiment of the presentinvention.

FIG. 2B a flow chart showing a process sequence for forming trench-viastructures in accordance with another embodiment of the presentinvention.

FIG. 3A is a flow chart showing a process sequence for removing portionsof dielectric material in accordance with one embodiment of the presentinvention.

FIG. 3B is a flow chart showing a process sequence for removing portionsof dielectric material in accordance with another embodiment of thepresent invention.

FIG. 4A is a flow chart showing a process sequence for forming adielectric layer having air gaps in accordance with one embodiment ofthe present invention.

FIG. 4B is a flow chart showing a process sequence for forming adielectric layer having air gaps in accordance with another embodimentof the present invention.

FIGS. 5A-5G schematically illustrate formation of a substrate stackhaving air gaps in accordance with one embodiment of the presentinvention.

FIGS. 6A-6C schematically illustrate formation of a substrate stackhaving air gaps in accordance with another embodiment of the presentinvention.

FIG. 7 schematically illustrates a substrate stack having trench viastructures formed using the process sequence of FIG. 2B.

FIGS. 8A-8B schematically illustrate formation of a substrate stackhaving air gaps in accordance with one embodiment of the presentinvention.

FIGS. 9A-9B schematically illustrate formation of a substrate stackhaving air gaps in accordance with one embodiment of the presentinvention.

FIG. 10 schematically illustrates relationships of air gap fraction witheffective dielectric constant and ratio of capacitance reduction for abarrier dielectric with k=5.1.

FIG. 11 schematically illustrates relationships of air gap fraction witheffective dielectric constant and ratio of capacitance reduction for abarrier dielectric with k=2.5.

To facilitate understanding, identical reference numerals have beenused, where possible, to designate identical elements that are common tothe figures. It is contemplated that elements disclosed in oneembodiment may be beneficially utilized on other embodiments withoutspecific recitation.

DETAILED DESCRIPTION

Embodiments of the present invention provide method for forming air gapsbetween conductive lines to reduce the dielectric constant k and toreduce RC delay in BEOL interconnects.

Embodiments of the present invention provide methods for forming airgaps in a trench level during fabrication of interconnects. The methodscomprise forming conductive lines in a porous low k dielectric material,then removing portions of the porous low k dielectric material to createtrenches around the conductive lines, and forming air gaps in thetrenches around the conductive lines while depositing a non-uniformdielectric material therein. Depending on the fraction of air gaps inthe dielectric material, the dielectric constant of the dielectricmaterial may be reduced by about 25% to about 50%. The methods of thepresent invention may extend utility of porous low k dielectric materialto fabricating devices with critical dimension of 22 nm and beyond. Themethods may be applied to any trench level and are economical to performbecause steps of forming air gaps are easily incorporated in to the flowof damascene process.

FIG. 1 is a flow chart showing a method 100 for forming air gaps ininterconnect in accordance with one embodiment of the present invention.BEOL interconnect generally includes multiple levels of interconnectstructures, typically including alternate trench layers and via layersof conductive materials and dielectrics. A trench layer generally refersto a dielectric film having conductive lines formed therein. A via layeris a layer of dielectrics having small metal vias that provideelectrical pathways from one trench layer to another trench layer. Themethod 100 may be applied in any level of the interconnects.

In step 110 of the method 100, a trench layer having metal structures ina low k porous dielectric material is formed. The trench layer may beformed by itself, for example above a contact layer of devices formed ina semiconductor substrate. In other cases, the trench layer may beformed along with a via layer using any suitable process sequences, forexample commonly used damascene process. The trench layer is generallyformed from a low k dielectric base which is removable for subsequentair gap formation. In one embodiment, the via layer is also formed inthe low k dielectric layer, as illustrated in a process sequence 110 ashown in FIG. 2A. In another embodiment, the via layer is formed in adifferent dielectric material, as illustrated in a process sequence 110b shown in FIG. 2B.

After the formation of the trench layer, selected portions of the low kporous dielectric may be removed so that reversed trenches are formedaround the metal structures in the trench layer, as shown in step 130.In one embodiment, the porous low k dielectric material may be removedby oxidizing controlled thickness of the porous low k dielectricfollowed by a wet etching step, as shown in a process sequence 130 a ofFIG. 3A. In another embodiment, when the trench layer and the via layerunderneath are formed in different dielectric materials, selectedregions of the low k porous material in the dielectric layer may beremoved by a masked etching process, as illustrated in a processsequence 130 b shown in FIG. 3B.

After removing the selected portion of the porous low k dielectricmaterial in the trench layer, air gaps may be formed in the reversedtrenches by deposition a non-conformal layer of a dielectric material,as shown in step 150 of FIG. 1. In one embodiment, the air gaps may beformed by depositing a non-conformal layer of dielectric barrier, asshown in a process sequence 150 a of FIG. 4A. In another embodiment, theair gaps may be formed while filling the reversed trenches with aninterlayer dielectric material, as shown in a process sequence 150 b ofFIG. 4B.

Upon the formation of the air gaps, fabrication of the trench layer iscompleted, a new layer of low k porous dielectric material may bedeposited and cured directly or indirectly on the trench layer, as shownin step 170 of FIG. 1.

In step 180, a new trench-via layer having metal structures may beformed in the new layer of low k porous dielectric material. Air gapsmay be formed in the new low k porous dielectric material using steps130 and 150 if so desired.

Air gaps may be formed in dielectric layers using the method 100.Different embodiments are available using combinations of differentprocess sequences for steps 110, 130, 150. Four exemplary embodimentsare described below.

Embodiment 1

FIGS. 5A-5G schematically illustrate formation of a substrate stack 200a having air gaps in accordance with one embodiment of the presentinvention. The substrate stack 200 a are formed using the processsequence 110 a of FIG. 2A, followed by the process sequence 130 a ofFIG. 3A, followed by the process sequence 150 a of FIG. 4A.

Referring to FIG. 5A, a via layer 202 and a trench layer 203 are formedon a preexisting layer 201, which includes a conductive line 210. FIG.2A illustrates a step 110 that may be used to form the via layer 202 andthe trench layer 203 as shown.

In step 111 of the process sequence 110 a, a dielectric barrier film 211is deposited all over the preexisting layer 201. The dielectric barrierfilm 211 is configured to prevent diffusion of conductive materials, forexample metals for the conductive line 210, into a subsequent dielectriclayer. The dielectric barrier film 211 generally comprises a barrierdielectric material, such as silicon nitride, silicon oxycarbide,amorphous hydrogenated silicon carbide, or nitrogen doped siliconcarbide (BLOk™).

In step 112, a porous low k dielectric material 212 is formed over thedielectric barrier film 211. The porous low k dielectric material 212has a thickness sufficient to form both the via layer 202 and the trenchlayer 203. Forming the porous low k dielectric material 212 generallycomprises depositing a silicon/oxygen containing material that furthercontains labile organic group, and curing the silicon/oxygen containingmaterial to form microscopic gas pockets that uniformly dispersed in thelayer. Curing the porous low k material 212 t may include electron beam(e-beam) treatments, ultraviolet (UV) treatments, thermal annealingtreatments (in the absence of an electron beam and/or UV treatment), andcombinations thereof.

The porous low k dielectric material 212 generally has a dielectricconstant lower than 2.5. Detailed description of exemplary methods forforming the porous low k dielectric material 212 may be found in theUnited States Patent Application Publication No. 2005/0233591, entitled“Techniques Promoting Adhesion of Porous Low K Film to UnderlyingBarrier Layer”, which is incorporated herein by reference.

In step 113, trench-via structures are formed in the porous low kdielectric material 212. The trench-via structures comprises trenches205 formed above vias 204 and may be formed using damascene methods.Exemplary methods for forming the trench-via structures in onedielectric layer may be found in the U.S. Pat. No. 6,753,258, entitled“Integration Scheme for Dual Damascene Structure”, which is incorporatedherein by reference.

In step 114, a metallic diffusion barrier 213 is lined on the surface ofthe trench-via structure. The metallic diffusion barrier 213 isconfigured to prevent diffusion between metal lines subsequentlydeposited in the trenches and the dielectric structures nearby. Themetallic diffusion barrier 213 may comprise tantalum (Ta) and/ortantalum nitride (TaN).

In step 115, the trench-via structures is filled with conductive lines214 comprising one or more metals. In one embodiment, a sputtering stepmay be performed to remove the metallic diffusion barrier 213 fromentire or portions of bottom walls of the trench-via structures, so thatthe conductive lines 214 may be in direct contact with the conductivelines 210 of the preexisting layer 201. Depositing the conductive lines214 may comprise forming a conductive seed layer and depositing a metalon the conductive seed layer. The conductive lines 214 may comprisecopper (Cu), aluminum (Al), or any suitable material with desirableelectrical conductivity.

In step 116, a chemical mechanical polishing (CMP) process is performedon the conductive lines 214, and the metallic diffusion barrier 213 sothat the porous low k dielectric 212 is exposed on a top surface 215 ofthe substrate stack 200 a, as shown in FIG. 5A.

Upon the formation the via layer 202 and the trench layer 203, portionsof the porous low k dielectric 212 in the trench layer 203 may beremoved so that air gaps may be formed between the conductive lines 214.

The process sequence 130 a shown in FIG. 3A may be used to remove theporous low k dielectric 212.

In step 131, a dense dielectric barrier film 216 is deposited over thetop surface 215, as shown in FIG. 5B. The dense dielectric barrier film216 is configured to prevent diffusion of metals, such as copper, in theconductive lines 214, and migration of wet etching chemistry to theconductive lines 214 in the subsequent process. The dense dielectricbarrier 216 may comprises a thin low k dielectric barrier film, such assilicon carbide (SiC), silicon carbide nitride (SiCN), boron nitride(BN), silicon boron nitride (SiBN), silicon boron carbide nitride(SiBCN), or combinations thereof.

In step 133, a hard mask layer 217 is deposited over the densedielectric barrier film 216, as shown in FIG. 5B. The hard mask layer217 is configured to provide patterning to the substrate stack in athermal process. The hard mask layer 217 may comprises silicon oxide.

In step 135, a pattern 219 is formed in the hard mask layer 217 and thedense dielectric barrier 216 using a photoresist 218, as shown in FIG.5B. The pattern 219 exposes only portions of the substrate where airgaps are desired. It is desirable to form air gaps in areas denselypacked with conductive lines. In one embodiment, air gaps may be formedin areas where the distance between neighboring conductive lines 214 isbetween about 100 nm to about 200 nm.

In step 137, an oxidizing process is performed to the porous low kdielectric material 212 exposed by the hard mask layer 217, as shown inFIG. 5C. In one embodiment, the oxidizing process may be performed bydispensing energy to the porous low k dielectric material 212 using anelectron beam (E-beam) in an ambient of inert gas and/or oxygen. E-beamtreated porous dielectric 220 has increased wet etching rate and may beselectively removed. Experiments have shown that E-beam treatment inaccordance with embodiments of the present invention may increase thewet etching rate (WER) of the low k porous dielectric material 212 byabout 100 times. For example, the etching rate of a porous low kdielectric material after UV curing (which forms nanosized air bubblesin the dielectric) is about 0.219 Å/min in a 100:1 dilute hydrogenfluoride (DHF) solution. While the same material after an E-beamtreatment may have a wet etch rate of about 30 Å/min in a 100:1 DHFsolution. Thus, the porous low k dielectric material 212 may beselectively removed using wet etching process after exposing selectedportion to the E-beam treatment.

An E-beam treatment apparatus generally includes a vacuum chamber, alarge-area cathode, a target or substrate to be treated located infield-free region, and an anode placed between the target and thecathode at a distance from the cathode that is less than the mean freepath length of electrons emitted therefrom. An E-beam apparatus furthercomprises a high voltage power supply connected to the cathode and a lowvoltage power supply connected to the anode.

During processing, gas in a space between the cathode and the target maybecome ionized to initiate electron emission. This occurs as a result ofnaturally occurring gamma rays, or emission can instead be initiatedartificially inside the chamber by a high voltage spark gap. Once thisinitial ionization takes place, positive ions are attracted to the anodeby a slightly negative voltage being applied to the anode. Thesepositive ions pass into an accelerating field region between the cathodeand the anode, and are accelerated towards the cathode surface as aresult of the high voltage applied to the cathode. Upon striking thesurface of the cathode, these high energy ions produce secondaryelectrons that are accelerated back toward the anode. Some of theseelectrons (which are now traveling mostly perpendicular to the cathodesurface) strike the anode, but many pass through the anode and continueon to the target, thus, performing an E-beam treatment to the substrate.Detailed description on apparatus and method for an E-beam treatment maybe found in U.S. Pat. No. 6,936,551, entitled “Method and Apparatus forE-beam Treatment Used to Fabricate Integrated Circuit Devices”, which isincorporated herein by reference. The E-beam treatment may be performedin an EBk™ electron beam chamber available from Applied Materials, Inc.of Santa Clara, Calif.

The E-beam treatment may be performed in an inert ambient, such asargon. In another embodiment, the E-beam treatment may also be performedin an oxygen environment, for example in an ambient of pure oxygen ormixture of inert gas and oxygen.

One embodiment of the present invention comprises controlling the depthof the E-beam treated porous dielectric 220. The depth of the E-beamtreated porous dielectric 220 is determined by the depth to whichimpinging electrons penetrate the dielectric layer before beingabsorbed. The depth generally depends on many factors (including theparticular material which is being treated). One of the most critical ofwhich is the energy of the electron beam as determined by theaccelerating voltage. In one embodiment of the present invention, thedepth of the E-beam treatment may be controlled using the followingequation:

$\begin{matrix}{{Depth} = \frac{0.046\left( V_{acc} \right)^{a}}{\rho}} & (1)\end{matrix}$

wherein Depth is treatment depth in Angstroms, Vacc is voltage appliedto the cathode in keV, a is a constant, and p is density of the filmbeing processed in gm/cm3. In one embodiment, for the porous low kdielectric material 212 having a dielectric constant k=2.35 and adensity of p=1.08 gm/cm3, the depth of treatment may be calculated usinga=1.80.

Alternatively, the oxidizing process may be performed by exposing theselected areas to ultra violet (UV) energy in an ambient with inert gasand/or oxygen gas.

In an optional step 139, a self-aligned capping layer 221 is formed onthe conductive lines 214, as shown in FIG. 5D. The self-aligned cappinglayer 221 may be formed using electroless deposition and formed only onthe exposed surface of the conductive lines 214. The self-alignedcapping layer 221 is configured to be a barrier to protect theconductive lines 214 from wet etching chemistry used in air gapformation and to prevent diffusion of species across an upper surface ofthe conductive lines 210. The self-aligned capping layer 221 may preventdiffusion of both copper and oxygen. For the conductive lines 214comprise copper, the self-aligned capping layer 221 may comprise avariety of compositions containing cobalt (Co), tungsten (W) ormolybdenum (Mo), phosphorus (P), boron (B), rhenium (Re), andcombinations thereof. Detailed descriptions for forming the self-alignedcapping layer 221 may be found in the United States Patent PublicationNo. 2007/0099417, entitled “Adhesion and Minimizing Oxidation onElectroless Co Alloy Films for Integration with Low k Inter-MetalDielectric and Etch Stop”, which are incorporated herein by reference.

In step 141, the E-beam treated porous dielectric 220 and the hard masklayer 217 are removed using a wet etching chemistry, as shown in FIG.5E. The wet etching chemistry may be a DHF solution. Other wet etchingchemicals, such as buffered hydrogen fluoride (BHF, NH₄F+HF+H₂O), mayalso be used. Exemplary etching methods may be found in U.S. Pat. No.6,936,183, entitled “Etch Process for Etching Microstructures”, which isherein incorporated by reference. After the removal of the E-beamtreated porous dielectric 220, reversed trenches 222 are formed betweenthe conductive lines 214.

Example for Curing and Etching

Copper conductive lines are formed in a nitrogen doped silicon dioxidelayer. The copper conductive lines are deposited in trenches with depthof about 257 nm. Distances between neighboring conductive lines areabout 88 nm. After CMP and masking, the nitrogen doped silicon dioxidelayer is cured by electron beam of 150 Dose. During electron beamcuring, argon is flown to the processing chamber at a flow rate of about50 sccm. The cured structure is the subjected to etching solution ofdiluted HF with a water/HF ratio of 100:1. The etch depth is about 150nm after 1 minute wet etching, about 180 nm after 2 minute wet etching,and about 190 nm about 3 minute wet etching.

After formation of the reversed trenches 222, one or more dielectricmaterial having air gaps may be filled in the reversed trenches 222. Theprocess sequence 150 a shown in FIG. 4A may be used to fill the reversedtrenches 222 and to form air gaps.

In step 151, the reversed trenches 222 are filled with a dielectricbarrier 223. Air gaps 224 are uniformly formed and sealed in thereversed trenches 222 during the deposition of the dielectric barrier223. The air gaps 224 are formed in the reversed trenches 222 due to thenon-conformality of the deposition process, wherein a deposition rate onthe side walls is relatively slow compared to the deposition rate nearthe entrance of the reversed trenches 222 “pinching off” the entrancebefore the reversed trenches 222 are filled and forming air gaps 224therein.

In one embodiment, the dielectric barrier 223 is the same or similar tothe dielectric barrier 216. The dielectric barrier 223 generally coversthe sidewalls of the reversed trenches 222 prior to pinch off providingbarrier against the diffusion of the conductive lines 214.

The dielectric barrier 223 may be deposited using PECVD. The depositionprocess of the dielectric barrier 223 is controlled so that bottoms andsidewalls of the reversed trenches 222 are covered prior to the pinchoff and the air gaps are uniformly height wise so that the subsequentCMP process does not break the air gaps 224. In one embodiment, theprocess may be controlled by adjusting chamber pressure, and/or biaspower in plasma generation. In another embodiment, the process may beadjusted by adjusting the shape and/or aspect ratio of the reversedtrenches to control the location of the air gaps 224.

The dielectric barrier 223 may comprise a dense low k, k=5.1, barrierdielectric. The presence of the air gaps 224 in the dielectric barrier223 reduces the effective dielectric constant of the dielectric materialbetween the conductive lines 214, thus reducing the capacitance betweenthe conductive lines 214. FIG. 10 schematically illustratesrelationships of air gap fraction with effective dielectric constant andratio of capacitance reduction for a barrier dielectric with k=5.1. Itis shown, the effective dielectric constant may be reduced to 2 and thecapacitance reduced by about 58% by introducing about 38% of air gaps inthe dielectric barrier 223 between the conductive lines 214.

In step 153, a CMP process is performed on the dielectric barrier 223 toremove excessive material and to achieve a planar top surface 225 forsubsequent trench and via layers, as shown in FIG. 5F. In oneembodiment, the dielectric barrier 223 may be planarized to have adesired thickness above the top surface 215 of the trench layer 203 sothat the dielectric barrier 223 provides barrier for subsequentinterlayer dielectric against the conductive lines 214 in the trenchlayer 203. In one embodiment, the planarization may be terminated priorto breaking into the air gaps 224. To avoid increasing thickness of thesubstrate stack, it is desired to control the height of the air gaps224.

Referring to FIG. 5G, a new interlayer dielectric 226, for example a newporous low k dielectric layer, is deposited on the top surface 225 ofthe dielectric barrier 223, as described in step 170 of FIG. 1. Vialayer 227 and trench layer 228 may be subsequently formed in the newinterlayer dielectric 226. Trench 230 and via 229 is then filled withconductive material. A new cycle of air gap formation may be performedon the trench layer 228 if desired.

It should be noted that air gaps generated using methods of the presentinvention do not have problems with unlanded vias, as shown in FIG. 5G.The via 229 does not completely land on the conductive lines 214 of thetrench layer 203. Portions of the via 229 is in contact with the porouslow k dielectric material 212. However, contacts between the unlandedportion of the via 229 and the air gaps 224 is avoidable because the airgaps only forms in a selected region.

Embodiment 2

FIGS. 6A-6C schematically illustrate formation of a substrate stack 200b having air gaps in accordance with one embodiment of the presentinvention. The substrate stack 200 b are formed using the processsequence 110 a of FIG. 2A, followed by the process sequence 130 a ofFIG. 3A, followed by the process sequence 150 b of FIG. 4B. The processsequence of the substrate stack 200 b is similar to that of thesubstrate stack 200 a prior to formation of air gaps and is illustratedin FIGS. 5A-5D.

After formation of the reversed trenches 222, one or more dielectricmaterial having air gaps may be filled in the reversed trenches 222. Theprocess sequence 150 b shown in FIG. 4B may be used to fill the reversedtrenches 222 and to form air gaps.

In step 155, the reversed trenches 222 are lined with a thin layer ofdielectric barrier material 240, as shown in FIG. 6A. In one embodiment,the dielectric barrier material 240 is the same or similar to thedielectric barrier 216. The dielectric barrier material 240 generallycovers the sidewalls of the reversed trenches 222 providing barrieragainst the diffusion of the conductive lines 214 for subsequentdielectric materials.

In step 157, the reversed trenches 222 are filled with an interlayerdielectric material 241, as shown in FIG. 6B. Air gaps 242 are uniformlyformed and sealed in the reversed trenches 222 during the deposition ofthe interlayer dielectric material 241. The air gaps 242 are formed inthe reversed trenches 222 due to the non-conformality of the depositionprocess, wherein a deposition rate on the side walls is relatively slowcompared to the deposition rate near the entrance of the reversedtrenches 222 “pinching off” the entrance before the reversed trenches222 are filled and forming air gaps 242 therein.

The interlayer dielectric 241 may be deposited using PECVD. Thedeposition process of the interlayer dielectric 241 is controlled sothat the air gaps 242 are formed from pinching off effect near theentrance of the reversed trenches 222. In one embodiment, the air gaps242 are uniform height wise so that the subsequent CMP process does notbreak the air gaps 242. In one embodiment, the process may be controlledby adjusting chamber pressure, and/or bias power in plasma generation.In another embodiment, the process may be adjusted by adjusting theshape and/or aspect ratio of the reversed trenches to control thelocation of the air gaps 242. A detailed description of formation of theinterlayer dielectric 242 may be found in the U.S. Pat. No. 6,054,379,entitled “Method of Depositing a Low K Dielectric with Organo Silane”,which is incorporated herein by reference.

The interlayer dielectric material 241 may comprise a low k, k=2.5,dielectric material. The presence of the air gaps 242 in the interlayerdielectric 241 reduces the effective dielectric constant of thedielectric material between the conductive lines 214, thus reducing thecapacitance between the conductive lines 214. FIG. 11 schematicallyillustrates relationships of air gap fraction with effective dielectricconstant and ratio of capacitance reduction for an interlayer dielectricwith k=2.5. It is shown, the effective dielectric constant may bereduced to k=2 and the capacitance reduced by about 20% by introducingabout 17% of air gaps in the interlayer dielectric 241 between theconductive lines 214.

In step 159, a CMP process is performed on the interlayer dielectric 241to remove excessive material and to achieve a planar top surface 243 forsubsequent, as shown in FIG. 6B. In one embodiment, the interlayerdielectric 241 may be planarized to have a desired thickness above thetop surface 215 of the trench layer 203 so that a subsequent via layermay be formed in the interlayer dielectric 241. In one embodiment, theplanarization may be terminated prior to breaking into the air gaps 242.To avoid increasing thickness of the substrate stack, it is desired tocontrol the height of the air gaps 242. In this embodiment, the top ofthe air gaps 242 may be at a higher position than the top surface 215 ofthe trench layer 203, because the interlayer dielectric 214 has athickness allowance of a via layer.

Referring to FIG. 6C, a new porous low k dielectric layer 246 isdeposited on the top surface 243 of the interlayer dielectric 241. A vialayer 244 is formed in the interlayer dielectric 241 and a trench layer245 is formed in the new porous dielectric layer 246. Trench-viastructures may then be filled with conductive material. A new cycle ofair gap formation may be performed on the trench layer 245 if desired.

Embodiment 3

FIG. 7 and FIGS. 8A-8B schematically illustrate formation of a substratestack 200 c having air gaps in accordance with one embodiment of thepresent invention. The substrate stack 200 c are formed using theprocess sequence 110 b of FIG. 2B, followed by the process sequence 130a of FIG. 3A, followed by the process sequence 150 b of FIG. 4B.

Referring to FIG. 7, a via layer 250 and a trench layer 251 are formedabove a preexisting layer 201, which includes a conductive line 210.FIG. 2B illustrates one process sequence 110 b that may be used to formthe via layer 250 and the trench layer 251 as shown.

In step 120 of the process sequence 110 b, a dielectric barrier film 252is deposited all over the preexisting layer 201. The dielectric barrierfilm 252 is configured to prevent diffusion of conductive materials, forexample metals for the conductive line 210, into a subsequent dielectriclayer. The dielectric barrier film 252 generally comprises a barrierdielectric material, such as silicon nitride, silicon oxycarbide, oramorphous hydrogenated silicon carbide (BLOk™).

In step 121, an interlayer dielectric material 253 is deposited abovethe dielectric barrier film 252. The interlayer dielectric material 253has a thickness enough to form the via layer 250 therein. The interlayerdielectric material 253 may comprises carbon doped silicon dioxide ornitrogen doped silicon dioxide. A detailed description of formation ofthe interlayer dielectric 253 may be found in the U.S. Pat. No.6,054,379, entitled “Method of Depositing a Low K Dielectric with OrganoSilane”, which is incorporated herein by reference.

In step 122, a porous low k dielectric material 254 is formed over theinterlayer dielectric 253. The porous low k dielectric material 254 hasa thickness enough to form the trench layer 251 therein.

In step 123, trench-via structures are formed in the interlayerdielectric material 253 and the porous low k dielectric material 254.

In step 124, a metallic diffusion barrier 255 is lined on the surface ofthe trench-via structure. The metallic diffusion barrier 255 isconfigured to prevent diffusion between metal lines subsequentlydeposited in the trenches and the dielectric structures nearby. Themetallic diffusion barrier 255 may comprise tantalum (Ta) and/ortantalum nitride (TaN).

In step 125, the trench-via structures is filled with conductive lines256 comprising one or more metals.

In step 126, a CMP process is performed on the conductive lines 256, themetallic diffusion barrier 255 so that the porous low k dielectric 254is exposed on a top surface 257, as shown in FIG. 7.

Upon the formation the via layer 250 and the trench layer 251, portionsof the porous low k dielectric 254 in the trench layer 251 may beremoved so that air gaps may be formed between the conductive lines 256using E-beam treatment via a pattern formed in a dielectric barrier 258and a hard mask 259. The process sequence 130 a shown in FIG. 3A may beused to remove the porous low k dielectric 254 forming reversed trenches260 as shown in FIG. 8A.

After formation of the reversed trenches 260, air gaps 263 may be formedusing the process sequence 150 a shown in FIG. 4A or the processsequence 150 b shown in FIG. 4B. FIG. 8B illustrates air gaps 263 formedusing the process sequence 150 b shown in FIG. 4B. A thin layer ofdielectric barrier 261 is lined in the reversed trenches 260. The airgaps 263 are formed in the reversed trenches 260 due to thenon-conformality of the deposition process of an interlayer dielectric262, wherein a deposition rate on the side walls is relatively slowcompared to the deposition rate near the entrance of the reversedtrenches 260 “pinching off” the entrance before the reversed trenches260 are filled.

Embodiment 4

FIG. 7 and FIGS. 9A-9B schematically illustrate formation of a substratestack 200 d having air gaps in accordance with one embodiment of thepresent invention.

As shown in FIG. 7, the via layer 250 and the trench layer 251 areformed using the process sequence 110 b of FIG. 2B. The via layer 250based on the interlayer dielectric 253. The trench layer 251 is based onthe porous low k dielectric layer 254.

Due to the property difference of the interlayer dielectric 253 and theporous low k dielectric layer 254, the interlayer dielectric 253 may beused as an etch stop while removing the porous low k dielectric layer254 to form reversed trenches 270, as show in FIG. 9A, and described instep 143 of process sequence 130 b. The reversed trenches 270 may beformed using a masked dry etching process to remove any porous low kdielectric 254 in selected regions.

After formation of the reversed trenches 270, air gaps 272 may be formedusing the process sequence 150 a shown in FIG. 4A or the processsequence 150 b shown in FIG. 4B. FIG. 9B illustrates air gaps 272 areformed in the reversed trenches 270 due to the non-conformality of thedeposition process of an interlayer dielectric 271, wherein a depositionrate on the side walls is relatively slow compared to the depositionrate near the entrance of the reversed trenches 270 “pinching off” theentrance before the reversed trenches 270 are filled.

In another embodiment, air gaps may be formed in trenches with slopedsidewalls to facilitate formation of air gaps. For example, air gaps maybe formed while filling dielectric materials in trenches that haveentrances narrower than bottoms. Detailed description regarding formingair gaps in trenches with sloped sidewalls may be found in U.S. patentapplication Ser. No. 11/869,409 (Attorney Docket No. 12054), filed Oct.9, 2007, entitled “Method for Forming an Air Gap in MultilevelInterconnect Structures”, which is incorporated herein by reference.

While the foregoing is directed to embodiments of the present invention,other and further embodiments of the invention may be devised withoutdeparting from the basic scope thereof, and the scope thereof isdetermined by the claims that follow.

1. A method for forming a dielectric structure having air gaps,comprising: depositing a first dielectric layer on a substrate;depositing a second dielectric layer on the first dielectric layer;forming trench-via structures in the first and second dielectric layer,wherein vias are formed in the first dielectric layer and trenches areformed in the second dielectric layer; filling the trench-via structureswith a conductive material; planarizing the conductive material toexpose the second dielectric layer; depositing a dielectric barrier filmon the conductive material and exposed second dielectric layer; forminga pattern in the dielectric barrier film and the hard mask layer toexpose selected regions of the substrate; removing the second dielectriclayer in the selected regions of the substrate to form reversed trenchesaround the conductive material filled in the trenches; and forming airgaps in the reversed trenches while depositing a third dielectricmaterial in the reversed trenches.
 2. The method of claim 1, whereindepositing the second dielectric layer comprises: depositing asilicon/oxygen containing material having labile organic group; andcuring the silicon/oxygen containing material to form microscopic gaspockets that uniformly dispersed in the first dielectric layer.
 3. Themethod of claim 1, wherein removing the second dielectric layercomprising etching the second dielectric layer exposed by the pattern.4. The method of claim 3, wherein the first dielectric layer and seconddielectric layer are different in property such that the firstdielectric layer serves as an etch stop during etching the seconddielectric layer.
 5. The method of claim 3, wherein etching the seconddielectric layer is performed using a masked dry etch process.
 6. Themethod of claim 1, further comprising lining the reversed trenches witha dielectric barrier prior to forming air gaps.
 7. The method of claim6, wherein the third dielectric material comprises a dielectric barriermaterial deposited non-conformally in the reversed trenches so that theair gaps are formed and sealed within the dielectric barrier material.8. The method of claim 6, wherein the third dielectric materialcomprises an interlayer dielectric material deposited non-conformally inthe reversed trenches so that the air gaps are formed and sealed withinthe interlayer dielectric material.
 9. The method of claim 1, whereinthe third dielectric material comprises a dielectric barrier materialdeposited non-conformally in the reversed trenches so that the air gapsare formed and sealed within the dielectric barrier material.
 10. Themethod of claim 9, further comprising polishing the third dielectricmaterial without breaking the air gaps.
 11. The method of claim 1,wherein the third dielectric material comprises an interlayer dielectricmaterial deposited non-conformally in the reversed trenches so that theair gaps are formed and sealed within the interlayer dielectricmaterial.
 12. The method of claim 11, further comprising polishing thethird dielectric material without breaking the air gaps.
 13. A methodfor forming a dielectric structure having air gaps, comprising:depositing an interlayer dielectric material layer on a substrate;depositing a porous dielectric layer on the interlayer dielectricmaterial layer; forming trench-via structures in the interlayerdielectric material layer and the porous dielectric layer; depositing ametallic diffusion barrier over the trench-via structure; filling thetrench-via structures with a conductive material; planarizing theconductive material to expose the porous dielectric layer; removing theporous dielectric layer in selected regions of the substrate to formreversed trenches around the conductive material filled in the trenches;and forming air gaps in the reversed trenches while depositing anon-conformal dielectric material in the reversed trenches.
 14. Themethod of claim 13, wherein depositing the porous dielectric layercomprises: depositing a silicon/oxygen containing material having labileorganic group; and curing the silicon/oxygen containing material to formmicroscopic gas pockets that uniformly dispersed in the porousdielectric layer.
 15. The method of claim 14, wherein removing theporous dielectric layer comprising etching the porous dielectric layerto expose the interlayer dielectric material layer.
 16. The method ofclaim 15, wherein the interlayer dielectric material layer and porousdielectric layer are different in property such that the interlayerdielectric material layer serves as an etch stop during etching of theporous dielectric layer.
 17. The method of claim 15, wherein thenon-conformal dielectric material comprises a dielectric barriermaterial deposited non-conformally in the reversed trenches so that theair gaps are formed and sealed within the dielectric barrier material.18. The method of claim 15, wherein the non-conformal dielectricmaterial comprises a dielectric barrier material depositednon-conformally in the reversed trenches so that the air gaps are formedand sealed within the dielectric barrier material.
 19. The method ofclaim 17, further comprising lining the reversed trenches with adielectric barrier prior to forming air gaps.
 20. The method of claim15, comprising polishing the non-conformal dielectric material withoutbreaking the air gaps.